The present invention relates to semiconductor device technology, and in particular relates to technology which is effective when applied to a semiconductor device having a nonvolatile memory.
As a nonvolatile semiconductor memory element (nonvolatile memory cell) capable of being electrically written and erased, an EEPROM (Electrically Erasable and Programmable Read Only Memory) is widely used. Such a nonvolatile memory cell has a structure (floating gate electrode structure) in which a conductive part in a floating state is provided beneath the gate electrode of an MIS (Metal Insulator Semiconductor) type field effect transistor (also called FET) (hereinafter, simply “MIS transistor”), or such a nonvolatile memory cell is constructed with an insulating film having a function to store a charge carrier (a carrier). The data write and data erase operations are achieved by storing an electric charge into the floating gate electrode or the charge storage film and controlling the injection or release of the electric charge to or from the charge storage region by means of the MIS structure.
As described above, when an electric charge is injected (or released) to (or from) the charge storage region, the threshold voltage of the MIS transistor will vary. In the MIS transistor, changes in the threshold voltage appear as differences in the drain current that flows in response to an applied gate voltage. With this amount of drain current of the MIS transistor, the charge storage state, i.e., the data retention state, can be read. The memory operation is achieved by the data write, erase, and read functions as described above.
As the insulating film having the charge storage function, a silicon nitride based insulating film (hereinafter, simply “silicon nitride film”) is known. The silicon nitride film formed over a semiconductor substrate will be a film that contains a lot of defects therein depending on the forming conditions. Such defects in the film will function as a carrier trap level. A charge trapped by such a trap level of the silicon nitride film is unlikely to leak out. For this reason, the nonvolatile memory using the silicon nitride film as the charge storage film is excellent in long-term data retention.
Furthermore, in order for a carrier trapped by the silicon nitride film not to easily leak out to the upper electrode or the lower substrate, a structure wherein both sides of the silicon nitride film are sandwiched by other insulating film is useful. For example, the so-called ONO (oxide/Nitride/oxide) insulating film, wherein both sides of a silicon nitride film are sandwiched by a silicon oxide based insulating film (hereinafter, simply “silicon oxide film”) or the like, is currently used. There is a nonvolatile memory cell that realizes the read operation by regarding this ONO insulating film as the gate insulating film of the MIS transistor. This cell employs gate electrode (Metal)/ONO insulating film/semiconductor substrate (Semiconductor) as the basic structure, and is referred to as the so-called MONOS type nonvolatile memory cell (hereinafter, simply “MONOS memory cell”).
For example, Japanese patent laid-open No. 2007-48882 (Patent Document 1) discloses technology, wherein in the process of manufacturing a MOS (Metal Oxide Semiconductor) FET (Field Effect Transistor), fluorine is ion-implanted after forming the gate electrode, thereby causing the fluorine to be present in the semiconductor interface or in the semiconductor surface. This technology can achieve an improvement in the operation speed of the semiconductor device, an improvement in the noise characteristic, an improvement in the characteristic defect rate, and the like.
Moreover, for example, Japanese patent laid-open No. 2000-236074 (Patent Document 2) discloses technology, wherein in the step of forming MISFETs constituting a DRAM (Dynamic Random Access Memory), a fluorine ion is implanted after forming the gate insulating film or after forming the gate electrode, thereby introducing fluorine in the interface between the gate insulating film and the semiconductor substrate.
Moreover, for example, Japanese patent laid-open No. 2005-197547 (Patent Document 3) discloses technology, wherein in the step of forming MOS transistors constituting a DRAM or an SRAM (Static Random Access Memory), a halogen element is ion-implanted and diffused into the source/drain diffusion layer.